D conversion

D/A conversion

There are two main methods, which are used to convert a digital value into an analog:

PWM (Pusle width modulation)
R2R ladder network

PWM (Pusle width modulation)

PWM is usually (but not always) done by a microcontroller. The conversion is done by varying the on- and off-times of a square wave. Then this signal is fed into a low-pass-filter which removes all high frequencies. The remaining signal is the analog value. (With a little ripple voltage of course, but it can be quite low.)

Lets assume that our rectangle signal has an amplitude of 5V and let us also assume that the on time is 30% of the period length (period length T=1/f) and the frequency is 1kHz:


   ^ U (voltage)
   |
   |
5V-|__.      .__.      .__.
   |  |      |  |      |  |
   |  |      |  |      |  |
   |  |      |  |      |  |
   |  |      |  |      |  |
   |  |      |  |      |  |
   |  |      |  |      |  |
0V-+------------------------------> t (time)
   |  |      |         |
   0  0.3ms  1ms       2ms

The output signal after the lowpass the signal is 0.3ms*Khz*5V=1.5V because the lowpass genrates an average value.
If you wanted output voltage of 3.5V, the duty cycle would have to be d=3.5V/5V=0.7 and the on-time 3.5V/(5V*1kHz)=0.7ms


   ^ U (voltage)
   |
   |
5V-|______.  .______.  .______.
   |      |  |      |  |      |
   |      |  |      |  |      |
   |      |  |      |  |      |
   |      |  |      |  |      |
   |      |  |      |  |      |
   |      |  |      |  |      |
0V-+------------------------------> t (time)
   |      |  |         |
   0      |  1ms       2ms
          0.7ms

A typical lowpass filter would look like this:


         R1          R2
  o----\/\/\/\--*--\/\/\/\--*--------o
                |           |
Input      C1 -----    C2 -----    Output
              -----       -----
                |           |
  o-------------*-----------*--------o

The components values depend on your PWM frequency.

Advantages
- Needs only 1 output pin of a microcontroller
- Only few (and cheap) external components
- Relatively high accuracy (up to 16Bit)
Disadvantages
- Consumes (most of the time) a timer of the microcontroller
- Accuracy depends on the timer width (8Bit, 10Bit, ...); may be solved by a more complex software
- Relatively slow, because of the time constant of the lowpass and the cutoff frequency

R2R ladder network

Another common used technic is the R2R ladder. The conversion is done by a simple resistor network.


                   R(1)          R(2)          R(3)
  .----------*---\/\/\/\---*---\/\/\/\---*---\/\/\/\---*-------------.
  |          |             |             |             |             |
  |          /             /             /             /             /
  o          \             \             \             \             \
  Uref       / 2R(1)       / 2R(2)       / 2R(3)       / 2R(4)       / 2R(5)
  o          \             \             \             \             \
  |          /             /             /             /             /
  |          |             |             |             |             |
 ---         |             |             |             |             |
              \             \             \             \           ---
           o   o         o   o         o   o         o   o
           |   |         |   |         |   |         |   |           Rf
           |   |         |   |         |   |         |   |    .---\/\/\/\---.
   .-------*-------------*-------------*-------------'   |    |             |
   |           |             |             |             |    |    |\       |
  ---          '-------------*-------------*-------------*----*----|-\      |
                                                                   |  \-----*---o Uout
                                                                   |  /         o
                                                              .----|+/          |
                                                              |    |/          ---
                                                              |
                                                             ---

The current which flows through 2R(1) is determined by U_ref. R(1) and 2R(2) is a voltage divider which has a resistive load connected to it, that has the value of 2R (the rest of the resistors). Therefore it halves the voltage U_ref. The half voltage produces the half current in 2R(2). The next resistors R(2) and 2R(3) are also a voltage divider, which has also a load of 2R connected to it so the voltage on 2R(3) is Uref/4 and the current through 2R(3) is one fourth if the current of 2R(1). The next two resistors ......
Do you see where it is going? The currents are either switched on the OP input or to ground. (Note that the OP input of the inverting amplifier acts like a virtual ground.). The currents are summed up by the OP which produces a negative output voltage - the analog value.
The switches are usually CMOS analog switches. It is also quite common to produce the currents with bipolar transistors. The R2R ladder can also be reversed: The switches put either ground of Uref on the ladder and instead of the Uref in the above circruit, there´s the output (take a look at the selfmade DA-converter half a page below). This works, because the U_refs, which are switched are divided down by the resistors more or less and summed up (by the network itself).

Advantages
- The conversion is done by the hardware (low software overhead)
- Relatively fast (depends).
Disadvantages
- Needs (most of the time) more output pins
- More (and mostly) more expensive components

A selfmade DA-converter


       74HC373
      .--------.
  D0--| 3     2|-------|\/\/\/\|-----*-------o Out
    D0|        |Q0        20k        |
      |        |                     \
      |        |                     / 10k
      |        |                     \
      |        |                     /
      |        |                     |
  D1--| 4     5|-------|\/\/\/\|-----*
    D1|        |Q1        20k        |
      |        |                     \
      |        |                     / 10k
      |        |                     \
      |        |                     /
      |        |                     |
  D2--| 7     6|-------|\/\/\/\|-----*
    D2|        |Q2        20k        |
      |        |                     \
      |        |                     / 10k
      |        |                     \
      |        |                     /
      |        |                     |
  D3--| 8     9|-------|\/\/\/\|-----*
    D3|        |Q3        20k        |
      |        |                     \
      |        |                     / 10k
      |        |                     \
      |        |                     /
      |        |                     |
  D4--|13    12|-------|\/\/\/\|-----*
    D4|        |Q4        20k        |
      |        |                     \
      |        |                     / 10k
      |        |                     \
      |        |                     /
      |        |                     |
  D5--|14    15|-------|\/\/\/\|-----*
    D5|        |Q5        20k        |
      |        |                     \
      |        |                     / 10k
      |        |                     \
      |        |                     /
      |        |                     |
  D6--|17    16|-------|\/\/\/\|-----*
    D6|        |Q6        20k        |
      |        |                     \
      |        |                     / 10k
      |        |                     \
      |        |                     /
    D7|        |Q7                   |
  D7--|18    19|-------|\/\/\/\|-----*
 GND--|10     1|--GND     20k        |
 +5V--|20    11|--CLK                \
      '--------'                     / 20k
                                     \
                                     /
                                     |
                                    ---

This D/A converter works with a reversed R2R ladder. All resistors should be 1%. The 74373 is a octal D-latch which stores the value to convert. First, the data byte (D0-D7) should be assigned. Afterwards, with the high transistion of CLK the value is stored into the latches and converted into an analog value by the resistors. You should use a 74HC or 74HCT (if you need TTL compatible inputs) series , because the CMOS logic has nearly 5V on high outputs and 0V on low outputs. Most TTL (or LSTTL) have only about 3.8V on high and 0.2V on low. Click here to read more about logic levels.
You´ll probably need a impendance converter (e.g. OP) at the output, because this circruit has a big ouput impendance.

A/D conversion

"Direct conversion" (Flash converters)
A/D conversion with D/A converters
Ramping methods
- Single slope
- Dual slope ("tracking")
Ramp generation methods
Sample & hold

"Direct conversion" (Flash converters)

If you wanted to build a 1Bit A/D converter, the simplest thing would be to use a comparator. Now, you can also use comparators if you want a better resolution.

^ Uref | | | \ / 1.5R \ / | | |\ .---------. *---|-\ | | | | \----| E | Uin | | / | | o----*-------|+/ | N | o-. | | |/ | | | | \ | C | --- | / R | | | \ | O | | / | | | | | D | | | |\ | | | *---|-\ | I | | | | \----| | | | | / | N | *-------|+/ | | | | |/ | G | | \ | | | / R | |---------o | \ | | Digital output | / | L |---------o | | | | | | |\ | O | | *---|-\ | | | | | \----| G | | | | / | | *-------|+/ | I | | | |/ | | | \ | C | | / R | | | \ | | | / | | | | | | | | |\ | | | *---|-\ | | | | | \----| | | | | / | | '-------|+/ '---------' | |/ \ / 0.5R \ / | | ---
The circriut on the left side works in a very simple way. It is a 2Bit A/D converter. The reference voltage Uref is divided down into 4 voltages. The comparators compare the input voltage with them. Once the input voltage is higher than the voltage on the comparator´s (-) input, its output goes high. If the input voltage rises, the bottom comparator is the first which goes high. Than the second from bottom and so on. The Logic encodes this into a binary 2Bit word.

A/D conversion with D/A converters

This way sounds a bit silly, but is quite widespread. It uses a comparator and a D/A converter.


       .-------.
----   |       |
    \  |       |
Input\ |  DAC  |           |\
word / |       |-----------|-\
    /  |       |           |  \--------o Uout
----   |       |           |  /
       '-------'    .------|+/
                    |      |/
                    |
      Uin o---------'
          o
          |
         ---

It works the following way: first, the DAC outputs the lowest voltage it can. If the state of the output is high, the input voltage is higher than the voltage outputted by the DAC. Now the DAC voltage is increased, till the output goes low. Now you know that the input voltage is a little bit lower than the actual input word (which is binary) and a little bit higher than the last input word. Now, you know how big you voltage is. That´s all.
You principially generate a digital voltage ramp at the output of the DAC. You can connect an upwards counter to it and use a microcontroller to start and reset the counter. If the clock comes from an accurate oscillator, you only have to measure the time the ramp voltage needs to reach U_in.

Ramping methods

Single slope: If the voltage rises and after you reached Uin you reset it (falls down to zero or whatever) it is called single slope.


U
^
|           .___________<--- Input voltage
|_______.   |   /|
|    /| |   |  / |
|   / | |___| /  |
|  /  |  /|  /   |<--- Ramp voltage
| /   | / | /    |
|/    |/  |/     |
+--------------------------> t

Dual slope (tracking): It is faster, if the voltage would rise and fall as the input voltage rises and falls. This method is called dual slope or tracking, because the compare voltage "tracks" the input voltage.
```
U
^
|         .___________<--- Input voltage
|_____.   |  /
|    /|\  | /<--- Ramp voltage
|   / |_\_|/
|  /
| /
|/
+--------------------------> t
```

Ramp generation methods

With a DAC. Alredy discribed in A/D conversion with D/A converters

Resistor-Capacitator ramp: The schematic is very simple. If the discharge input is high, the current flows through the resistor R1 and over the transistor to ground. Uramp remains at 0V. If the discharge input goes low, the current charges the capacitator. The main disavantage of this circruit is, that Uramp follows the equation: U_ramp=U_ref*(1-e^(-t/(R1*C)))
(Where e=2.71828182846)
```
(Transistor is a NPN Type)
               R1
 o----------\/\/\/\----*-----*-------o
Uref                   |     |      Uramp
 o--.        R2      |/C   -----     o
    |   o--\/\/\/\---|     ----- C   |
    |   Discharge    |\E     |       |
    |   o              |     |       |
    |   |              |     |       |
   --- ---            ---   ---     ---
```
If you use too big capacitators, the transistor may be damaged. Also use a capacitator with a low temperature coefficient and leakage current.

Capacitator with current source: This circruit works by charging a capacitator with a constant current. The main advantage is, that the equation is simply: Uramp=(Iconst*t)/C


   ^ +Ub   ^ +Ub
   |       |
 .---.     |
  \ / D1   \
   V       / R2
  ---      \
   |       /
 .---.     |
  \ / D2   |
   V       |
  ---   PNP|
   |  T1 |/E   .-----------o
   *-----|     |           Uramp
   |     |\C   |           o
   |       |   |           |
   |       v I |           |
   |       |   |           |
   |       *---*---.NPN   ---
   \    C  |       C\| T2
 R1/     -----       |----\/\/\/\---o
   \     -----     E/|      R3      Discharge
   /       |       |                o
   |       |       |                |
  ---     ---     ---              ---

Again, if you use a too big capacitator, the transistor T₂ may be damaged. Big capacitators cause also a long discharge time. Also use a capacitator with a low temperature coefficient and leakage current. I wouldn´t let go Uramp up to +U_b, because then the U_CE of T₁ gets very low and may cause a nonlinearity.
(T1: e.g. BC558B, T2: e.g. BC548).
I = (U_D1 + U_D2 - U_BET1)/R₂
I_B = I/B
R₁ = (+U_b - 2*U_D)/(15*q) q = about 15*I_B; bigger q gives a better stability

Sample & hold

The best A/D converter doens´t help you much without a Sample and hold circruit, because the input voltage isn´t allowed to change during a conversion cycle. Otherwise you get a wrong result. A sample and hold is circruit, which can "freeze" a voltage.
Look at this schematic. It is the a basic sample and hold circruit:


                                    .---------.
                                    |         |
    .---------.                     |   |\    |
    |         |                     '---|-\   |
    |   |\    |  .--------.             |  \--*------o
    '---|-\   |  |   /    |             |  /        Uout
        |  \--*--|--/ L---|------*------|+/          o
        |  /     |        |      |      |/           |
 o------|+/      '--------'    -----                 |
Uin     |/           | S1      -----                 |
 o         ____ o----'           | C                 |
 |         Hold/Sample           |                   |
 |              o                |                   |
 |              |                |                   |
---            ---              ---                 ---

The two OPs are impendance converters. The input voltage U_in appears at the output of the first OP. If the switch S₁ is closed, the capacitator is charged to the voltage U_in. If the input voltage changes, after a short time the capacitator has the same voltage. The second OP buffers the capacitator´s voltage to the output. Once the switch opens, the capacitator is disconnected from the output of the first OP, but it still holds the input voltage from the moment when the switch opened, so the output voltage doesn´t change any more C should be a cap with a low leakage current.

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